Krishna Seshan, editor of the Handbook of Thin Film Deposition is seeking a contributor to write a chapter on Scaling for the third edition.
If this role might be of interest to you – or if you want to recommend someone who might be a candidate to write the chapter, please contact Krishna via this blog or by e-mail:
krishna.seshan@gmail.com

We are also inviting Comments to this blog posting regarding Krishna’s discussion points on Scaling, which follow:

1. What should be included in a general discussion of the scaling of semiconductor devices?
Early pioneers (G.,Moore and R. Dennard and coworkers) were quick to see that transistor dimensions could shrink provided the scaling obeyed some fundamental physical laws. The rules they derived applied to channel length scaling, gate oxide thickness scaling and device density. As a result both Vt the threshold voltage for the transistor to turn on decreases and switching speeds double per generation. Tables showing the now famous Dennard scaling and graphs showing Moore’s law scaling will be included.

The immediate result is that the whole industry has a “road map” that allows development of many of the supportive details like lithography, deposition equipment etc.

2. Does scaling affect the choice of thin films used and the deposition techniques used ?
Starting from the Input Output layers. In the early days most I/O was through wire bonded pads. The speed, and inductance increases - consequences of scaling-made it necessary to use low inductance Lead Bump or C4 technology originally developed by IBM. More recently environmental mandates have made it necessary to use Pb free solders.

The Back End interconnect has seen the most changes in thin film materials. The old Al and Si-Al metallurgy with CVD oxide has too much Resistance , Capacitance and lack of scalability -needing different via materials with many registration and lithography issues- to be able to survive. There has been a sea change to Copper Damascene metallurgy where the copper is electro-deposited. The oxide is replaced with low K. fluroinated oxide to reduce dielectric constant.

At the Front End (transistor and first level interconnect) there have been a number of changes. Perhaps the most challenging areas are in new Gate Oxide materials which need to have a very high dielectric constant, needs to be very thin ( 35 nm or less) have integrity , be robust and reliable. At the transistor level, the channel is now tuned for uni axial stress to enhance mobility and new Si-Ge films are used.

These are examples of how scaling affects the choice of thin film materials.

3. What are the key topics that need to be covered in a chapter on Scaling?

Front End - scaling factor k
What Device Parameters Scale?
Transistor Gate Length and Gate oxide thickness decrease as k;
Device capacitance increase as oxide thickness decreases.
Vt drops.
Electrical And Other Effects
Switching Speeds increase as 1/k**2 ; electric field conservation and Coulomb Law obeyed.
Described by Dennard scaling laws.

Mid Section
What Device Parameters Scale?
Contact dimensions- registration tolerances decrease as i/k.
Electrical And Other Effects
Resistance and capacitance and RC have to be kept at minimum;

Interconnect and mid section
Number of layers increase ; up to 12 or 13 layers have been reported.
What Device Parameters Scale?
If new materials are not selected carefully RC would increase cross talk and noise would increase. Copper and low K has avoided this pitfall.
Electrical And Other Effects
Pitch- R, C, Cross talk noise increased current densities, electromigration.

Input and output
What Device Parameters Scale?
Number of Input and Output bumps. Power delivery and removal of processed signals.
Electrical And Other Effects
Described by Rent's rule.

Thermal Scaling
What Device Parameters Scale?
This affects the power consumed by the device
Electrical And Other Effects
See papers of Ravi Mahajan etc.

Scaling and Reliability
Electrical And Other Effects
Thermo-mechanical Effects

4. Any new insights into scaling ? What about role of mechanical stress ?
(Krishna: "These are discussions I have had with Bill Baerg")
One area which we have found that is not discussed very much is Thermo-mechanical stress and the scaling of overall stress as devices get smaller. However workers in the industry are well aware of stress effects. It has been know that many films when deposited and cooled become compressive -while others are tensile. This has been used in designing the uniaxial stress in transistors to increase hole mobility. (Thomson - Maistry - Bohr papers).

While testing for device reliability the stress related effects lead to stress cracking of nitrides leading to loss of hermiticty ( various patents on nitrides Seshan - et al); Stress corrosion , filament growth are also stress driven failure mechanisms.

Lastly electromigration is enhanced by stress, and stress is an integral part of Black's equation.

How will stress scale ? What are its effects. We plan to write a brief introduction to Thermo-mechanical stress. We welcome any comments and suggestions.

5. What are present thoughts on Thermal Scaling?
Ravi Mahajan and others have proposed that there is a pattern to thermal scaling. Their papers will be cited in the discussion.

6. Scaling of several different Semiconductor Devices
Of the most common devices , Flah or Non-Volatile Memory, Static and Dynamic RAM (DRAM & SRAM) - and Microprocessors, Flash scaling is the most dramatic. This technology uses the smalled transistors in the Industry; further each cell is now capable of storing multiple bits. A discussion of these various devices their trends and challenges they pose to thin films will be included.

Comments from Chris Petti:
It's arguable that NAND flash is currently the technology driver in the IC world -- that is, the world's smallest transistors (or at least the world's densest arrays of transistors) are in NAND devices. Thus, any discussion on scaling should include the details peculiar to NAND: data retention, endurance, and others. Thin film issues (gate dielectrics, storage films [poly or nitride], etc.) are paramount here.
Another way NAND "scales" is to put multiple electrical bits on a single physical bit -- multi-level cells are pretty standard now. These cells put even more constraints on the physical scaling issues mentioned above.

7. Any thoughts on 3D Scaling
Chris Petti: You ask about 3D scaling: the book chapter we wrote (for Springer; came out in 2007) discusses the different monolithic 3D techniques in detail, but 2D scaling has always been able to outdo 3D on cost, until recently. The key to 3D scaling of memory cells, or logic gates, is that each level must be extremely simple to construct. This explains the interest in stacking cross-point memory cells on top of each other.

Krishna Seshan, editor of the ‘Handbook of Thin Film Deposition’ is seeking a contributor to write a chapter on Scaling for the third edition. If this role might be of interest to you – or if you want to recommend someone who might be a candidate to write the chapter, please contact Krishna via this blog or by e-mail:
krishna.seshan@gmail.com

We are also inviting Comments to this blog posting regarding Krishna’s discussion points on Scaling, which follow:

1. What should be included in a general discussion of the scaling of semiconductor devices?
Early pioneers (G.,Moore and R. Dennard and coworkers) were quick to see that transistor dimensions could shrink provided the scaling obeyed some fundamental physical laws. The rules they derived applied to channel length scaling, gate oxide thickness scaling and device density. As a result both Vt the threshold voltage for the transistor to turn on decreases and switching speeds double per generation. Tables showing the now famous Dennard scaling and graphs showing Moore’s law scaling will be included.

The immediate result is that the whole industry has a “road map” that allows development of many of the supportive details like lithography, deposition equipment etc.

2. Does scaling affect the choice of thin films used and the deposition techniques used ?
Starting from the Input Output layers. In the early days most I/O was through wire bonded pads. The speed, and inductance increases - consequences of scaling-made it necessary to use low inductance Lead Bump or C4 technology originally developed by IBM. More recently environmental mandates have made it necessary to use Pb free solders.

The Back End interconnect has seen the most changes in thin film materials. The old Al and Si-Al metallurgy with CVD oxide has too much Resistance , Capacitance and lack of scalability -needing different via materials with many registration and lithography issues- to be able to survive. There has been a sea change to Copper Damascene metallurgy where the copper is electro-deposited. The oxide is replaced with low K. fluroinated oxide to reduce dielectric constant.

At the Front End (transistor and first level interconnect) there have been a number of changes. Perhaps the most challenging areas are in new Gate Oxide materials which need to have a very high dielectric constant, needs to be very thin ( 35 nm or less) have integrity , be robust and reliable. At the transistor level, the channel is now tuned for uni axial stress to enhance mobility and new Si-Ge films are used.

These are examples of how scaling affects the choice of thin film materials.

3. What are the key topics that need to be covered in a chapter on Scaling?

Front End - scaling factor k
What Device Parameters Scale?
Transistor Gate Length and Gate oxide thickness decrease as k;
Device capacitance increase as oxide thickness decreases.
Vt drops.
Electrical And Other Effects
Switching Speeds increase as 1/k**2 ; electric field conservation and Coulomb Law obeyed.
Described by Dennard scaling laws.

Mid Section
What Device Parameters Scale?
Contact dimensions- registration tolerances decrease as i/k.
Electrical And Other Effects
Resistance and capacitance and RC have to be kept at minimum;

Interconnect and mid section

Number of layers increase ; up to 12 or 13 layers have been reported.
What Device Parameters Scale?
If new materials are not selected carefully RC would increase cross talk and noise would increase. Copper and low K has avoided this pitfall.
Electrical And Other Effects
Pitch- R, C, Cross talk noise increased current densities, electromigration.

Input and output
What Device Parameters Scale?
Number of Input and Output bumps. Power delivery and removal of processed signals.
Electrical And Other Effects
Described by Rent's rule.

Thermal Scaling
What Device Parameters Scale?
This affects the power consumed by the device
Electrical And Other Effects
Papers of Ravi Mahajan etc.

Scaling and Reliability
Electrical And Other Effects
Thermo-mechanical Effects

4. Any new insights into scaling ? What about role of mechanical stress ?
(Krishna: "These are discussions I have had with Bill Baerg")
One area which we have found that is not discussed very much is Thermo-mechanical stress and the scaling of overall stress as devices get smaller. However workers in the industry are well aware of stress effects. It has been know that many films when deposited and cooled become compressive -while others are tensile. This has been used in designing the uniaxial stress in transistors to increase hole mobility. (Thomson - Maistry - Bohr papers).

While testing for device reliability the stress related effects lead to stress cracking of nitrides leading to loss of hermiticty ( various patents on nitrides Seshan - et al); Stress corrosion , filament growth are also stress driven failure mechanisms.

Lastly electromigration is enhanced by stress, and stress is an integral part of Black's equation.

How will stress scale ? What are its effects. We plan to write a brief introduction to Thermo-mechanical stress. We welcome any comments and suggestions.

5. What are present thoughts on Thermal Scaling?

Q&A with 3rd edition Editor, Krishna Seshan

How is this handbook different from the other titles already available?
First this is not a pedagogical text dealing with the fundamentals of thin film deposition. Such material is much better covered by more specialized books. Rather this is a Handbook written by practicing engineers and process designers - those who are developing integrated thin film processes. My handbook provides information about process integration and an understanding of how thin films work together to provide high yield reliable semiconductor products. So the chapters are more about the process of developing architectures of various thin films that work together in an integrated device environment.

What are we looking for by way of new chapters and contributors?
We are looking for potential practicing engineers who would like to write about their specialties.
We would like to see chapters dealing with the evolution of lithography and its role in thin film choices. We would like to see a chapter on multilayer high K dielectric gates for gate technology. We would like to see chapters dealing with new materials like Chalgogenides which are being considered for flash and memory applications.

How can prospective authors contact you?
Other than posting to this blog, I would invite new authors to contact me direct:
Krishna Seshan (krishna.seshan@gmail com), Editor of Handbook of Thin Film Deposition, 3rd edition

Intro to the Handbook of Thin Film Deposition - by Krishna Seshan

The Handbook of Thin Film Deposition 1st Ed was edited by W. Schuegraf and W. Kerns and was published by Noyes Publications in 1980s. It had classic material like a chapter on Wafer Cleaning by Werner Kerns, an extensive chapter on Silicon Epi by Martin Hammond etc. These chapters were written by the early developers of these techniques that have now become standard practice in the Industry.

The 2nd Edition was published in 2002, and took into account significant developments in the thin film architecture of silicon devices. Chapters on the practicality of wafer processing, maintaining high yeilds, and contamination control were added. However the book did not have a chapter on Cu interconnect.

The 3rd edition will have new chapters that include a description of the the low K dielectric and Cu interconnect metallurgy and the various thin film manufacturing steps needed for it s manufacture. This will include a chapter on chemical mechanical polishing. Coverage of various reliability issues in Cu interconnect metallurgy is planned.

In addition there has been a spawning of new and related devices: solar thin films, many thin film applications leading to the inclusion of radio frequency devices to enable wireless in handheld devices, and developments that wil lead to the inclusion of lasers and light as part of the device function. So a new section called Emerging Technologies will be added.

Lastly we are fortunate to be able to include a chapter on Optical Thin Films by Angus McCloud of the Thin Film Center, in anticipation of the integration of optics and optical components into semiconductors.