Krishna Seshan, editor of the ‘Handbook of Thin Film Deposition’ is seeking a contributor to write a chapter on Scaling for the third edition. If this role might be of interest to you – or if you want to recommend someone who might be a candidate to write the chapter, please contact Krishna via this blog or by e-mail:
krishna.seshan@gmail.com

We are also inviting Comments to this blog posting regarding Krishna’s discussion points on Scaling, which follow:

1. What should be included in a general discussion of the scaling of semiconductor devices?
Early pioneers (G.,Moore and R. Dennard and coworkers) were quick to see that transistor dimensions could shrink provided the scaling obeyed some fundamental physical laws. The rules they derived applied to channel length scaling, gate oxide thickness scaling and device density. As a result both Vt the threshold voltage for the transistor to turn on decreases and switching speeds double per generation. Tables showing the now famous Dennard scaling and graphs showing Moore’s law scaling will be included.

The immediate result is that the whole industry has a “road map” that allows development of many of the supportive details like lithography, deposition equipment etc.

2. Does scaling affect the choice of thin films used and the deposition techniques used ?
Starting from the Input Output layers. In the early days most I/O was through wire bonded pads. The speed, and inductance increases - consequences of scaling-made it necessary to use low inductance Lead Bump or C4 technology originally developed by IBM. More recently environmental mandates have made it necessary to use Pb free solders.

The Back End interconnect has seen the most changes in thin film materials. The old Al and Si-Al metallurgy with CVD oxide has too much Resistance , Capacitance and lack of scalability -needing different via materials with many registration and lithography issues- to be able to survive. There has been a sea change to Copper Damascene metallurgy where the copper is electro-deposited. The oxide is replaced with low K. fluroinated oxide to reduce dielectric constant.

At the Front End (transistor and first level interconnect) there have been a number of changes. Perhaps the most challenging areas are in new Gate Oxide materials which need to have a very high dielectric constant, needs to be very thin ( 35 nm or less) have integrity , be robust and reliable. At the transistor level, the channel is now tuned for uni axial stress to enhance mobility and new Si-Ge films are used.

These are examples of how scaling affects the choice of thin film materials.

3. What are the key topics that need to be covered in a chapter on Scaling?

Front End - scaling factor k
What Device Parameters Scale?
Transistor Gate Length and Gate oxide thickness decrease as k;
Device capacitance increase as oxide thickness decreases.
Vt drops.
Electrical And Other Effects
Switching Speeds increase as 1/k**2 ; electric field conservation and Coulomb Law obeyed.
Described by Dennard scaling laws.

Mid Section
What Device Parameters Scale?
Contact dimensions- registration tolerances decrease as i/k.
Electrical And Other Effects
Resistance and capacitance and RC have to be kept at minimum;

Interconnect and mid section

Number of layers increase ; up to 12 or 13 layers have been reported.
What Device Parameters Scale?
If new materials are not selected carefully RC would increase cross talk and noise would increase. Copper and low K has avoided this pitfall.
Electrical And Other Effects
Pitch- R, C, Cross talk noise increased current densities, electromigration.

Input and output
What Device Parameters Scale?
Number of Input and Output bumps. Power delivery and removal of processed signals.
Electrical And Other Effects
Described by Rent's rule.

Thermal Scaling
What Device Parameters Scale?
This affects the power consumed by the device
Electrical And Other Effects
Papers of Ravi Mahajan etc.

Scaling and Reliability
Electrical And Other Effects
Thermo-mechanical Effects

4. Any new insights into scaling ? What about role of mechanical stress ?
(Krishna: "These are discussions I have had with Bill Baerg")
One area which we have found that is not discussed very much is Thermo-mechanical stress and the scaling of overall stress as devices get smaller. However workers in the industry are well aware of stress effects. It has been know that many films when deposited and cooled become compressive -while others are tensile. This has been used in designing the uniaxial stress in transistors to increase hole mobility. (Thomson - Maistry - Bohr papers).

While testing for device reliability the stress related effects lead to stress cracking of nitrides leading to loss of hermiticty ( various patents on nitrides Seshan - et al); Stress corrosion , filament growth are also stress driven failure mechanisms.

Lastly electromigration is enhanced by stress, and stress is an integral part of Black's equation.

How will stress scale ? What are its effects. We plan to write a brief introduction to Thermo-mechanical stress. We welcome any comments and suggestions.

5. What are present thoughts on Thermal Scaling?